publications

A 16Kb one-time-programmable (OTP) antifuse memory is fabricated in a 5nm high-K, metal-gate FinFET CMOS for the first time. The bootstrap high voltage scheme (BHVS), read endpoint detection (REPD) and pseudo-differential sensing (PDS) are implemented to achieve intrinsic bit error rate (BER) below 1ppb for in-field programming in 5nm SoC and 10 years of data retention at 125°C.

The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique, tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end, this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally, temperature coefficient compensation for time constant is accomplished by poly resistors and a V TH -tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/−0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.

Recent research has shown subthreshold operation to reduce active energy in low-power MCUs [1], [2], [5]. However, some applications impose additional constraints. For battery-powered sensor nodes deployed in remote locations, the MCU may lie dormant for long periods, only waking up when a sensor detects activity. For such cases, the MCU needs very low sleep power to maximize battery lifetime, deterministic real-time response to capture rare sensor events, and energy-efficient operation with enough compute and memory to run useful workloads. This work shows a 65nm Arm Cortex-M33 SoC for constrained battery-powered sensor nodes achieving 10 nW sleep power (4 KB$ retention) with fine-grained DVFS and performance regulation from 0.8 MHz (0.40 V) to 38 MHz (0.75V) to address a range of real-time requirements across the operating range of 0-to-85° C and 1.0-to-1.5V battery voltage. Digital circuit optimizations reduce active power to 47μ W (20pJ/cycle) on a high-activity keyword spotting (KWS) workload.

The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique, tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end, this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally, temperature coefficient compensation for time constant is accomplished by poly resistors and a V TH -tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/−0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.

The pulse-width modulated (PWM) switching rectification that can achieve a high power factor (PF) for increasing the energy transfer efficiency between an LC resonator and a rectifier and voltage step-up and -down conversion is proposed for a wireless power transfer (WPT) receiver. The proposed method can emulate the switching rectifier as a resistive load by using an inductor and integrated phase synchronizers. Additionally, similar to a switched-inductor converter that controls the duty cycle ratio (D), the proposed PWM rectifier can control the output voltage VOUT when the input is a rectified, wirelessly coupled voltage instead of a constant voltage. Thus, unlike a conventional PWM switching rectifier for ac mains, an additional voltage conditioning circuit would not be needed after the proposed rectifier for WPT. The proposed PWM switching rectification is implemented in the AMS 0.18 μm 1.8 V/5 V CMOS process. PF = 1 is measured, indicating the most efficient energy transfer, compared to only 0.55-0.65 in a peak detection rectifier. Additionally, 88.2% of peak power conversion efficiency of the switching rectifier is achieved, and the maximum output power is 80.3 mW at 500 kHz of the WPT frequency. Moreover, the measured voltage conversion ratios ranging between 0.73× and 2× are demonstrated in this paper.

The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique, tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end, this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally, temperature coefficient compensation for time constant is accomplished by poly resistors and a V TH -tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/−0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.

This paper presents a low-input-voltage (100 mV), low-output-voltage (500-600 mV) thermoelectric energy harvesting interface circuit for near-threshold energy-efficient Internet-of-Things (IoT) devices. The capacitive bootstrapping technique is used to generate a positive and negative bias pair for alleviating the significant conduction losses of power MOSFETs in a near-threshold operation. Internal bias voltages are automatically boosted to different levels as per the loading conditions to extend the output power range. The deployment of constant on-time digital pulse skip modulation with digital zero current detection (ZCD) achieves an ultralight load operation, and precluding a reverse current. The digital ZCD is capable of dynamically adjusting the off-time (TOFF) of the power transistors, which vary according to the input and output voltage levels. The proposed step-up dc-dc power converter implemented using a 180 nm CMOS technology demonstrates a maximum conversion efficiency of 76.4% over a 1 μW-500 μW load range, significantly evaluating the feasibility of the near-threshold interface circuit architecture for energy-efficient IoT devices.

This paper investigates a high power factor switch-based wireless power transfer front-end circuit for heterogeneous systems. This circuit uses an integrated switching rectifier, implemented in 0.18um 1.8V/5V CMOS process. An integrated pair of phase synchronizers is used to align the waveshape of a wirelessly-coupled sinusoidal voltage source in the receiving coil to the corresponding conducting current. Using this approach, the power factor can be increased above 0.9 without requiring any wireless or wired feedback to the transmitter. The integrated switching rectifier can also provide: ac-dc rectification; facilitate the deployment of multi-receiver to single-transmitter wireless power transfer; and have the capability for voltage up and down conversion of the peak amplitude of the sinusoidal voltage source by use of a pulse-width modulation controller. From measured results, the output voltage can be stepped down from 1.65V to 1.08V and stepped up from 1.5V to 1.68V. Also, the measured power factor is 0.9 when the conducting current is managed at continuous conduction mode.

This paper presents a 100 mV input, 500 mV output single-inductor multiple-output (SIMO) based step-up dc-dc converter with adaptive gate biasing (AGB) technique implemented in 0.18 μm CMOS technology for thermoelectric energy harvesting. The proposed AGB technique and near-threshold voltage (near- VTH) energy redistribution control (ERC) ensure high conversion efficiency over a wide range of load currents. The proposed method automatically reduces conduction and switching losses of power MOSFETs without the need for auxiliary power converters or additional off-chip inductors. The AGB technique reduces conduction and switching losses under heavy-load and light-load conditions, respectively. The experimental results show that the efficiency of the proposed converter is enhanced by 25.5% and 18% at output load currents of 1500 μA and 50 μA, respectively. The proposed step-up dc-dc converter achieves the lowest output voltage and provides the highest conversion efficiency of 83.4% to date in standard CMOS process for thermoelectric energy harvesting.

Energy harvesting techniques have been developed more than a decade and received much attention in realizing long-term energy autonomous microsystems. Many converter topologies and circuit techniques have been reported to effectively convert the harvested energy to usable outputs. In this paper, major green energy sources as well as the equivalent circuits are reviewed. In addition, maximum power point tracking (MPPT) technique and power conversion topologies are also included.

The embedded fully self-biased switched-capacitor (FSBSC) with single-inductor high voltage bipolar-output (SIHBO) converter is proposed to achieve the energy and area-efficient driving scheme for the paper-like cholesteric liquid crystal display (Ch-LCD), which becomes the next generation of electronic readers in the consumer markets. As the compact power management module, SIHBO converter can provide +/-35V bipolar outputs for row driving. Besides, the embedded FSBSC is utilized to generate the different voltage levels for modulating the gray-color in column driving scheme. This combination carries out the effective driving operation for Ch-LCD through the demand of timing control unit. Experimental results show the achievement of +/-35V output voltage in the SIHBO converter and the variety voltage levels generated from FSBSC. The peak efficiency is up to 84% with the silicon area of 6.53 mm2.

The paper-like cholesteric liquid crystal display (Ch-LCD) has become the next generation of electronic readers in consuming market. The embedded fully symmetric self-biased switched-capacitor (FSSBSC) with single-inductor high voltage bipolar-output (SIHBO) converter is proposed to achieve the energy and area-efficient driving scheme. As the compact power management module, SIHBO converter can provide +/−35V bipolar outputs for row driving. In addition, the embedded FSSBSC is utilized to generate the different voltage levels for modulating the gray-color in column driving scheme. This combination carries out the effective driving operation for Ch-LCD through the demand of timing control unit. Simulated results show the achievement of +/-35V output voltage in the SIHBO converter and the variety voltage levels generated from FSSBSC. The peak efficiency is derived of 85% with the integrated chip area of 6.53 mm2.

A near-zero cross-regulation (near-zero CR) single-inductor bipolar-output (SIBO) converter with an adaptive-energy correlation (AEC) control is proposed as a compact power management solution for driving cholesteric-LCD (Ch-LCD). The SIBO converter can provide a pair of positive and negative output voltages with only one external inductor for achieving the polarity reversion operation in Ch-LCD to obtain high-quality displays. The proposed AEC control decides energy distribution for bipolar outputs without any cross regulation through the embedded prediction function. The chip fabricated in a 0.25 μm CMOS process demonstrates near-zero cross-regulation at bipolar outputs with 90% peak power conversion efficiency.

Cholesteric liquid-crystal display (Ch-LCD) has the bi-stable characteristic to achieve the energy-saving for the green technology. Backlight is even unnecessary in the Ch-LCD system. The single-inductor bipolar-output (SIBO) converter is one of best candidate to supply the power management function for the Ch-LCD with dual positive and negative output voltages by using a single inductor for a compact solution. The energy control methodology with the current-mode control and the power conservation mechanism (PCM) can strengthen the voltage quality to get high display quality. The test chip fabricated by 0.25 μm CMOS technology demonstrates the non-noticeable cross-regulation at dual outputs with 90 % peak power conversion efficiency.

This paper presents a high integrated dual-side dual-output (DSDO) switched-capacitor (SC) regulator with only two flying capacitors. Generally, a dual-phase voltage doubler and an inverter are used to supply positive and negative voltage for TFT-LCD gate drivers, respectively. Four flying capacitors, eight pin-outs, and sixteen power switches are necessary for their operations in the driver integrated chip (IC). The proposed DSDO SC regulator combines both dual-phase voltage doubler and inverter converter into one channel through the use of time multiplexing technique at the cost of little performance degradation. As a result, it not only diminishes the number of flying capacitor from four to two but also removes four IC pin-outs for low cost and compact size. Beside, sixteen necessary power switches are reduced to twelve for decreasing about 27% silicon area.

The Avalanche Photodiodes (APDs) are widely used in a variety of optical application requiring high sensitivity, such as long-distance optical communication and optical distance measurement, because the APDs can detect the low level light. APDs accompanied with the Transimpedance Amplifier (TIA) are utilized on the receiver side in the communication system. The trend of integrating the active optical components faces the challenge of integrating different voltage levels. In general, the operation voltage of TIA is usually 1.8 V or 3.3 V. However, the APD requires a high reverse-biasing voltage of 40 V 80 V. Therefore, a high conversation-ratio boost converter must be included to provide the high voltage to bias the APD. Besides, output voltage ripple must be minimized to decrease the influence on communication signals. Experimental results show the 80 V output voltage boosted from the input voltage of 2.5 V. The output voltage ripple is 2 mV under the condition of 1 mA load current.

This paper proposed a single inductor bipolar outputs (SIBO) switching converter for the active matrix Organic Light-Emitting Diode (AMOLED). The negative voltage is generated by the inverting buck-boost converter, which is regulated by the high signal-to-noise ratio comparator. Moreover, the boost converter is utilized to provide the positive output voltage. The proposed switching converter uses the switch sequential to reduce the positive voltage ripple to about 5 mV with the proportional-integral (PI) compensator to guarantee good line and load-regulation. Simulation results show the positive output voltage is regulated to 5 V and the negative output voltage is -7 V for driving the AMOLED. When the load current is 25 mA and the ESR is 30 mΩ, the output voltage ripples are equal to 5 mV and 11 mV for positive and negative voltages, respectively. Besides, the load and line regulations of positive output voltage are 0.24 mV/mA and 5 mV/V, respectively. The maximum efficiency is 88.5% when the input voltage is 4.5 V and the load current is 50 mA.

A single-inductor multiple positive- and negative-output (SIMPNO) converter provides a compact-size and high efficiency solution for electronic paper displays (EPDs) system. With the single inductor multiple output structure, an adaptive current control methodology with the proposed vector current control mode (VCCM) can wisely minimize the current tolerance to be smaller than 10% between input and all outputs. Additionally, owing to the VCCM technique for adequate inductor current control, the cross regulation is smaller than 0.35 V/A. The test chip was fabricated by 0.25 μm BCD process with a peak value of 90% at heavy loads.

Electronic paper display (EPD) shows the trend of state-of-the-art display technique. It not only holds image/text without consuming energy but also presents thin and flexibility like ordinary paper. Single-inductor multi-output (SIMO) converter, with innovative multi-vector current-control methodology, precisely tracks and quantifies the actual demanded-energy and addresses excessive-energy for power-efficient and space-minimized requirements of EPDs. The testing chip occupies 0.45 mm2 in 0.25 μm CMOS technology and achieves the power conversion efficiency larger than 85 % at the order of 0.5 m W output power.

In a complete theory there is an element corresponding to each element of reality. A sufficient condition for the reality of a physical quantity is the possibility of predicting it with certainty, without disturbing the system. In quantum mechanics in the case of two physical quantities described by non-commuting operators, the knowledge of one precludes the knowledge of the other. Then either (1) the description of reality given by the wave function in quantum mechanics is not complete or (2) these two quantities cannot have simultaneous reality. Consideration of the problem of making predictions concerning a system on the basis of measurements made on another system that had previously interacted with it leads to the result that if (1) is false then (2) is also false. One is thus led to conclude that the description of reality as given by a wave function is not complete.